HD6432351 Datasheet, PDF (799/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

A.6 Condition Code Modification
This section indicates the effect of each CPU instruction on the condition code. The notation used
in the table is defined below.
m = 31 for longword operands
15 for word operands
7 for byte operands
Si
The i-th bit of the source operand
Di The i-th bit of the destination operand
Ri
The i-th bit of the result
Dn The specified bit in the destination operand
— Not affected
Modified according to the result of the instruction (see definition)
0
Always cleared to 0
1
Always set to 1
*
Undetermined (no guaranteed value)
Z'
Z flag before instruction execution
C'
C flag before instruction execution
779