HD6432351 Datasheet, PDF (594/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Figure 13-11 shows an example of SCI operation for transmission using the multiprocessor
format.
Start
1 bit
0 D0 D1
Data
Multi-
proce-
ssor Stop
bit bit
Start
bit
Data
Multi-
proces- Stop
sor bit bit 1
D7 0/1 1 0 D0 D1
D7 0/1
1 ^{Idle state}
(mark state)
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
and TDRE flag cleared to
0 in TXI interrupt service
routine
TXI interrupt
request generated
1 frame
TEI interrupt
request generated
Figure 13-11 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
• Multiprocessor serial data reception
Figure 13-12 shows a sample flowchart for multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
574