HD6432351 Datasheet, PDF (353/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

9.3.3 Pin Functions
Port 2 pins also function as PPG output pins (PO7 to PO0) and TPU I/O pins (TIOCA3, TIOCB3,
TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5). Port 2 pin functions are shown in
table 9-5.
Table 9-5 Port 2 Pin Functions
Pin
Selection Method and Pin Functions
P2₇/PO7/TIOCB5
The pin function is switched as shown below according to the combination of
the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in
TIOR5, bits CCLR1 and CCLR0 in TCR5, bit NDER7 in NDERL, and bit
P27DDR.
TPU Channel
5 Setting
Table
Below (1)
Table Below (2)
P27DDR
—
0
1
1
NDER7
—
—
0
1
Pin function
TIOCB5
output
P2₇
input
P2₇
output
PO7
output
TIOCB5 input *
Note: * TIOCB5 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 = 1.
TPU Channel
5 Setting
MD3 to MD0
IOB3 to IOB0
CCLR1,
CCLR0
Output
function
(2)
(1)
(2)
B'0000, B'01xx B'0010
B'0000 B'0001 to —
B'0100 ^B'0011
B'1xxx ^{B'0101 to}
B'0111
—
—
—
—
Output
—
compare
output
(2)
B'xx00
(1)
(2)
B'0011
Other than B'xx00
—
Other B'10
than B'10
—
PWM
—
mode 2
output
x: Don’t care
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