HD6432351 Datasheet, PDF (539/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in
interval timer mode. This flag cannot be set during watchdog timer operation.
Bit 7
OVF
0
1
Description
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
(Initial value)
[Setting condition]
Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF
signal when TCNT overflows.
Bit 6
WT/IT
Description
0
Interval timer: Sends the CPU an interval timer interrupt request (WOVI)
when TCNT overflows
(Initial value)
1
Watchdog timer: Generates the WDTOVF signal when TCNT overflows
Note: * For details of the case where TCNT overflows in watchdog timer mode, see section 12.2.3,
Reset Control/Status Register (RSTCSR).
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME
0
1
Description
TCNT is initialized to H'00 and halted
TCNT counts
(Initial value)
Bits 4 and 3—Reserved: Read-only bits, always read as 1.
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