HD6432351 Datasheet, PDF (506/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and
counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing
takes precedence.
Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
ø
TCNT input
clock
TCNT
Counter
clear signal
TGF
TCFV
H'FFFF
Disabled
H'0000
Figure 10-56 Contention between Overflow and Counter Clearing
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