HD6432351 Datasheet, PDF (934/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

P1_n
*
Reset
R
Q
D
P1nDDR
C
WDDR1
Reset
R
Q
D
P1nDR
C
WDR1
RDR1
PPG module
Pulse output enable
Pulse output
TPU module
Output compare output/
PWM output enable
Output compare output/
PWM output
RPOR1
Legend
WDDR1 : Write to P1DDR
WDR1 : Write to P1DR
RDR1 : Read P1DR
RPOR1 : Read port 1
n = 2, 3, 5, 7
Input capture input
External clock input
Note: * Priority order: Output compare output/PWM output > pulse output > DR output
Figure C-1 (b) Port 1 Block Diagram (Pins P1₂, P1₃, P1₅, and P1₇)
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