HD6432351 Datasheet, PDF (569/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) (cont)
Bit Rate
(bit/s)
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
ø = 14 MHz
ø = 14.7456 MHz
ø = 16 MHz
ø = 17.2032 MHz
Error
Error
Error
Error
n
N
(%) n
N
(%) n
N
(%) n
N
(%)
2
248 –0.17 3
64 0.70 3
70 0.03 3
75 0.48
2
181 0.16 2
191 0.00 2
207 0.16 2
223 0.00
2
90 0.16 2
95 0.00 2
103 0.16 2
111 0.00
1
181 0.16 1
191 0.00 1
207 0.16 1
223 0.00
1
90 0.16 1
95 0.00 1
103 0.16 1
111 0.00
0
181 0.16 0
191 0.00 0
207 0.16 0
223 0.00
0
90 0.16 0
95 0.00 0
103 0.16 0
111 0.00
0
45 –0.93 0
47 0.00 0
51 0.16 0
55 0.00
0
22 –0.93 0
23 0.00 0
25 0.16 0
27 0.00
0
13 0.00 0
14 –1.70 0
15 0.00 0
16 1.20
0
10 — 0
11 0.00 0
12 0.16 0
13 0.00
Bit Rate
(bit/s)
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
ø = 18 MHz
ø = 19.6608 MHz
Error
Error
n
N
(%) n
N
(%) n
3
79 –0.12 3
86 0.31 3
2
233 0.16 2
255 0.00 3
2
116 0.16 2
127 0.00 2
1
233 0.16 1
255 0.00 2
1
116 0.16 1
127 0.00 1
0
233 0.16 0
255 0.00 1
0
116 0.16 0
127 0.00 0
0
58 –0.69 0
63 0.00 0
0
28 1.02 0
31 0.00 0
0
17 0.00 0
19 –1.70 0
0
14 –2.34 0
15 0.00 0
ø = 20 MHz
Error
N
(%)
88 –0.25
64 0.16
129 0.16
64 0.16
129 0.16
64 0.16
129 0.16
64 0.16
32 –1.36
19 0.00
15 1.73
549