HD6432351 Datasheet, PDF (70/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 2-3 Instructions Classified by Function (cont)
Type
Block data
transfer
instruction
Instruction
EEPMOV.B
Size*
—
EEPMOV.W —
Function
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block according to parameters set in
general registers R4L or R4, ER5, and ER6.
R4L or R4: size of block (bytes)
ER5: starting source address
ER6: starting destination address
Execution of the next instruction begins as soon as the
transfer is completed.
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