HD6432351 Datasheet, PDF(780/989 Page) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

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HD6432351 Datasheet, PDF (780/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

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Table A-5 Number of Cycles in Instruction Execution (cont)

Instruction

EEPMOV

EXTS

EXTU

INC

JMP

JSR

LDC

LDM

LDMAC

Branch

Instruction Address

Fetch

Read

Stack Byte Data

Operation Access

Mnemonic

EEPMOV.B

I

J

K

L

2

2n+2 *2

EEPMOV.W

2

2n+2 *2

EXTS.W Rd

1

EXTS.L ERd

1

EXTU.W Rd

1

EXTU.L ERd

1

INC.B Rd

1

INC.W #1/2,Rd

1

INC.L #1/2,ERd

1

JMP @ERn

2

JMP @aa:24

2

JMP @@aa:8

Normal

2

1

Advanced 2

2

JSR @ERn

Normal

2

1

Advanced 2

2

JSR @aa:24

Normal

2

1

Advanced 2

2

JSR @@aa:8

Normal

2

1

1

Advanced 2

2

2

LDC #xx:8,CCR

1

LDC #xx:8,EXR

2

LDC Rs,CCR

1

LDC Rs,EXR

1

LDC @ERs,CCR

2

LDC @ERs,EXR

2

LDC @(d:16,ERs),CCR

3

LDC @(d:16,ERs),EXR

3

LDC @(d:32,ERs),CCR

5

LDC @(d:32,ERs),EXR

5

LDC @ERs+,CCR

2

LDC @ERs+,EXR

2

LDC @aa:16,CCR

3

LDC @aa:16,EXR

3

LDC @aa:32,CCR

4

LDC @aa:32,EXR

4

LDM.L @SP+, (ERn-ERn+1)

2

4

LDM.L @SP+, (ERn-ERn+2)

2

6

LDM.L @SP+, (ERn-ERn+3)

2

8

LDMAC ERs,MACH

Cannot be used in the H8S/2350 Series

LDMAC ERs,MACL

Word Data Internal

Access Operation

M

N

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

760

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