HD6432351 Datasheet, PDF (231/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

7.3 Register Descriptions (2) (Full Address Mode)
Full address mode transfer is performed with channels A and B together. For details of full address
mode setting, see table 7-4.
7.3.1 Memory Address Register (MAR)
Bit
:
MAR
:
Initial value :
R/W
:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————
00000000* * * ** * **
— — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W
Bit
:
MAR
:
Initial value :
R/W
:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
* * * * * * * * * * * * * * **
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
*: Undefined
MAR is a 32-bit readable/writable register; MARA functions as the transfer source address
register, and MARB as the destination address register.
MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are
reserved: they are always read as 0, and cannot be modified.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the
source or destination memory address can be updated automatically. For details, see section 7.3.4,
DMA Control Register (DMACR).
MAR is not initialized by a reset or in standby mode.
7.3.2 I/O Address Register (IOAR)
IOAR is not used in full address transfer.
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