HD6432351 Datasheet, PDF (369/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Port 5 Data Direction Register (P5DDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
— P53DDR P52DDR P51DDR P50DDR
Initial value : Undefined Undefined Undefined Undefined 0
0
0
0
R/W
:
—
—
—
—
W
W
W
W
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 5. Bits 7 to 4 are reserved. P5DDR cannot be read; if it is, an undefined value will be
read.
Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P5DDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port 5 Data Register (P5DR)
Bit
:
7
6
5
4
3
—
—
—
— P53DR
Initial value : Undefined Undefined Undefined Undefined 0
R/W
:
—
—
—
—
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
0
P50DR
0
R/W
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P5₃ to P5₀).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
P5DR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port 5 Register (PORT5)
Bit
:
7
6
5
4
3
2
1
0
—
—
—
—
P53
P52
P51
P50
Initial value : Undefined Undefined Undefined Undefined —*
—*
—*
—*
R/W
:
—
—
—
—
R
R
R
R
Note: * Determined by state of pins P53 to P50.
PORT5 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 5 pins (P5₃ to P5₀) must always be performed on P5DR.
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