HD6432351 Datasheet, PDF (21/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Section 1 Overview
1.1 Overview
The H8S/2350 Series is a series of microcomputers (MCUs: microcomputer units), built around
the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral
functions on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include DMA controller (DMAC)
and data transfer controller (DTC) bus masters, ROM (H8S/2351 only) and RAM memory, a16-bit
timer-pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial
communication interface (SCI), A/D converter, D/A converter, and I/O ports.
The H8S/2351 has on-chip mask ROM.
The H8S/2351 supports seven operating modes (modes 1 to 7), while the H8S/2350 supports three
operating modes (modes 1, 4, and 5). There is a choice of address space and single-chip mode or
expansion mode.
The features of the H8S/2350 Series are shown in Table 1-1.
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