HD6432351 Datasheet, PDF (133/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

5.4.5 Interrupt Response Times
The H8S/2350 Series is capable of fast word transfer instruction to on-chip memory, and the
program area is provided in on-chip ROM* and the stack area in on-chip RAM, enabling high-
speed processing.
Table 5-9 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5-9 are explained in table 5-10.
Note: * Only applies to the H8S/2351.
Table 5-9 Interrupt Response Times
Normal Mode
Advanced Mode
No. Execution Status
INTM1 = 0 INTM1 = 1 INTM1 = 0 INTM1 = 1
1 Interrupt priority determination*¹
3
3
3
3
2 Number of wait states until executing 1 to
instruction ends*²
19+2·S_I
3 PC, CCR, EXR stack save
2·S_K
4 Vector fetch
S_I
5 Instruction fetch*³
2·S_I
6 Internal processing*⁴
2
1 to
19+2·S_I
3·S_K
S_I
2·S_I
2
1 to
19+2·S_I
2·S_K
2·S_I
2·S_I
2
1 to
19+2·S_I
3·S_K
2·S_I
2·S_I
2
Total (using on-chip memory)
11 to 31 12 to 32 12 to 32 13 to 33
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8 Bit Bus
16 Bit Bus
Symbol
Internal 2-State
Memory Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch
S_I 1
4
6+2m
2
3+m
Branch address read
S_J
Stack manipulation
S_K
Legend
m : Number of wait states in an external device access.
113