HD6432351 Datasheet, PDF (548/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
12.5.4 System Reset by WDTOVF Signal
If the WDTOVF output signal is input to the RES pin of the H8S/2350 Series, the H8S/2350
Series will not be initialized correctly. Make sure that the WDTOVF signal is not input logically
to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown
in figure 12-9.
Reset input
H8S/2350 Series
RES
Reset signal to entire system
WDTOVF
Figure 12-9 Circuit for System Reset by WDTOVF Signal (Example)
12.5.5 Internal Reset in Watchdog Timer Mode
The H8S/2350 Series is not reset internally if TCNT overflows while the RSTE bit is cleared to 0
during watchdog timer operation, but TCNT and TSCR of the WDT are reset.
TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that
a read of the WOVF flag is not recognized during this period. To clear the WOVF falg, therefore,
read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
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