HD6432351 Datasheet, PDF (600/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

• Serial data transmission (clocked synchronous mode)
Figure 13-16 shows a sample flowchart for serial transmission.
The following procedure should be used for serial data transmission.
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE= 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
All data transmitted?
Yes
Read TEND flag in SSR
TEND= 1
Yes
No
[3]
No
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit data
empty interrupt (TXI) request and data
is written to TDR.
Clear TE bit in SCR to 0
<End>
Figure 13-16 Sample Serial Transmission Flowchart
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