HD6432351 Datasheet, PDF (16/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

12.2.1 Timer Counter (TCNT)......................................................................................... 518
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 518
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 520
12.2.4 Notes on Register Access...................................................................................... 522
12.3 Operation............................................................................................................................ 524
12.3.1 Watchdog Timer Operation .................................................................................. 524
12.3.2 Interval Timer Operation ...................................................................................... 525
12.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 525
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).......................... 526
12.4 Interrupts ............................................................................................................................ 527
12.5 Usage Notes ....................................................................................................................... 527
12.5.1 Contention between Timer Counter (TCNT) Write and Increment...................... 527
12.5.2 Changing Value of CKS2 to CKS0 ...................................................................... 527
12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 528
12.5.4 System Reset by WDTOVF Signal ...................................................................... 528
12.5.5 Internal Reset in Watchdog Timer Mode ............................................................. 528
Section 13 Serial Communication Interface (SCI) ..................................................... 529
13.1 Overview............................................................................................................................ 529
13.1.1 Features ................................................................................................................. 529
13.1.2 Block Diagram...................................................................................................... 531
13.1.3 Pin Configuration.................................................................................................. 532
13.1.4 Register Configuration.......................................................................................... 533
13.2 Register Descriptions ......................................................................................................... 534
13.2.1 Receive Shift Register (RSR) ............................................................................... 534
13.2.2 Receive Data Register (RDR)............................................................................... 534
13.2.3 Transmit Shift Register (TSR).............................................................................. 535
13.2.4 Transmit Data Register (TDR).............................................................................. 535
13.2.5 Serial Mode Register (SMR) ................................................................................ 536
13.2.6 Serial Control Register (SCR) .............................................................................. 539
13.2.7 Serial Status Register (SSR) ................................................................................. 543
13.2.8 Bit Rate Register (BRR) ....................................................................................... 546
13.2.9 Smart Card Mode Register (SCMR)..................................................................... 555
13.2.10 Module Stop Control Register (MSTPCR)........................................................... 556
13.3 Operation............................................................................................................................ 557
13.3.1 Overview............................................................................................................... 557
13.3.2 Operation in Asynchronous Mode........................................................................ 559
13.3.3 Multiprocessor Communication Function ............................................................ 570
13.3.4 Operation in Clocked Synchronous Mode............................................................ 578
13.4 SCI Interrupts ..................................................................................................................... 586
13.5 Usage Notes ....................................................................................................................... 588
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