HD6432351 Datasheet, PDF (690/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

20.3 Medium-Speed Mode
When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-
speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on
the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0 bits. The bus
masters other than the CPU (the DMAC and DTC) also operate in medium-speed mode. On-chip
supporting modules other than the bus masters always operate on the high-speed clock (ø).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is
made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made
to software standby mode. When software standby mode is cleared by an external interrupt,
medium-speed mode is restored.
When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is
cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 20-1 shows the timing for transition to and clearance of medium-speed mode.
ø,
supporting module clock
Bus master clock
Medium-speed mode
Internal address bus
SCKCR
SCKCR
Internal write signal
Figure 20-1 Medium-Speed Mode Transition and Clearance Timing
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