HD6432351 Datasheet, PDF (186/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.5.9 Byte Access Control
When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the
control signals required for byte access.
When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6-18 shows the
control timing in the 2-CAS system, and figure 6-19 shows an example 2-CAS system DRAM
connection.
When only DRAM with a ×8 configuration is connected, set the CW2 bit to 1 in MCR.
T_p
T_r
ø
A₂₃ to A₀
Row
T_c1
T_c2
Column
CSn (RAS)
CAS
Byte control
LCAS
HWR (WE)
Note: n = 2 to 5
Figure 6-18 2-CAS System Control Timing (Upper Byte Write Access)
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