HD6432351 Datasheet, PDF (385/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Port B Data Register (PBDR) [H8S/2351 Only]
Bit
:
Initial value :
R/W
:
7
PB7DR
0
R/W
6
5
PB6DR PB5DR
0
0
R/W R/W
4
3
2
PB4DR PB3DR PB2DR
0
0
0
R/W R/W R/W
1
0
PB1DR PB0DR
0
0
R/W R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB₇ to PB₀).
PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port B Register (PORTB) [H8S/2351 Only]
Bit
:
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Initial value :
—*
—*
—*
—*
—*
—*
—*
—*
R/W
:
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PB7 to PB0.
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port B pins (PB₇ to PB₀) must always be performed on PBDR.
If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B
read is performed while PBDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin
states, as PBDDR and PBDR are initialized. PORTB retains its prior state after a manual reset, and
in software standby mode.
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