HD6432351 Datasheet, PDF (152/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.2.5 Bus Control Register L (BCRL)
Bit
:
Initial value :
R/W
:
7
6
5
BRLE BREQOE —
0
0
1
R/W
R/W
R/W
4
LCASS
1
R/W
3
DDS
1
R/W
2
1
0
— WDBE WAITE
1
0
0
R/W R/W R/W
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, the LCAS signal, DMAC single address transfer, enabling or disabling of the write
data buffer function, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Description
External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports.
(Initial value)
External bus release is enabled.
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus release state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE
0
1
Description
BREQO output disabled. BREQO can be used as I/O port.
BREQO output enabled.
(Initial value)
Bit 5—Reserved: Only 1 should be written to this bit.
Bit 4—LCAS Select (LCASS): Write 0 to this bit when using the DRAM interface.
LCAS pin used for 2-CAS type DRAM interface LCAS signal. BREQO output and WAIT input
cannot be used when LCAS signal is used.
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