HD6432351 Datasheet, PDF (469/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

10.4.4 Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 10-5 shows the register combinations used in buffer operation.
Table 10-5 Register Combinations in Buffer Operation
Channel
0
3
Timer General Register
TGR0A
TGR0B
TGR3A
TGR3B
Buffer Register
TGR0C
TGR0D
TGR3C
TGR3D
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10-16.
Compare match signal
Buffer register
Timer general
register
Comparator
TCNT
Figure 10-16 Compare Match Buffer Operation
449