HD6432351 Datasheet, PDF (642/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

15.1.2 Block Diagram
Figure 15-1 shows a block diagram of the A/D converter.
Module data bus
Internal data bus
AVCC
Vref
AVSS
10-bit D/A
A AAA
D DDD
D DDD
R RRR
A B CD
AA
DD
CC
SR
R
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADTRG
+
–
Comparator
Sample-and-
hold circuit
Control circuit
ø/8
ø/16
ADI
interrupt
Conversion start
trigger from TPU
ADCR : A/D control register
ADCSR : A/D control/status register
ADDRA : A/D data register A
ADDRB : A/D data register B
ADDRC : A/D data register C
ADDRD : A/D data register D
Figure 15-1 Block Diagram of A/D Converter
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