HD6432351 Datasheet, PDF (142/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.1.3 Pin Configuration
Table 6-1 summarizes the pins of the bus controller.
Table 6-1 Bus Controller Pins
Name
Address strobe
Read
High write/write enable
Low write
Chip select 0
Chip select 1
Chip select 2/row address
strobe 2
Chip select 3/row address
strobe 3
Chip select 4/row address
strobe 4
Chip select 5/row address
strobe 5
Chip select 6
Chip select 7
Symbol I/O
AS
Output
RD
Output
HWR Output
LWR Output
CS0 Output
CS1 Output
CS2 Output
CS3 Output
CS4 Output
CS5 Output
CS6 Output
CS7 Output
Function
Strobe signal indicating that address output
on address bus is enabled.
Strobe signal indicating that external space
is being read.
Strobe signal indicating that external space
is to be written, and upper half (D₁₅ to D₈) of
data bus is enabled.
2-CAS DRAM write enable signal.
Strobe signal indicating that external space
is to be written, and lower half (D₇ to D₀) of
data bus is enabled.
Strobe signal indicating that area 0 is
selected.
Strobe signal indicating that area 1 is
selected.
Strobe signal indicating that area 2 is
selected.
DRAM row address strobe signal when
area 2 is in DRAM space.
Strobe signal indicating that area 3 is
selected.
DRAM row address strobe signal when
area 3 is in DRAM space.
Strobe signal indicating that area 4 is
selected.
DRAM row address strobe signal when
area 4 is in DRAM space.
Strobe signal indicating that area 5 is
selected.
DRAM row address strobe signal when
area 5 is in DRAM space.
Strobe signal indicating that area 6 is
selected.
Strobe signal indicating that area 7 is
selected.
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