HD6432351 Datasheet, PDF (333/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Section 9 I/O Ports
9.1 Overview
The H8S/2350 Series has 12 I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port
(port 4).
Table 9-1 summarizes the port functions. The pins of each port also have other functions.
Each port includes a data direction register (DDR) that controls input/output (not provided for the
input-only port), a data register (DR) that stores output data, and a port register (PORT) used to
read the pin states.
Ports A to E in the H8S/2351 have a built-in pull-up MOS function, and in addition to DR and
DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input
pull-up.
Port 3, and port A in the H8S/2351, have an open-drain control register (ODR) that controls the
on/off state of the output buffer PMOS.
Ports A to E can drive a single TTL load and 90 pF capacitive load, and ports 1, 2, 3, 5, 6, F, and
G can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington
transistor when in output mode. Ports 1, A, B, and C can drive an LED (10 mA sink current).
Port 2, and pins 6₄ to 6₇ and A₄ to A₇, are Schmitt-triggered inputs.
For block diagrams of the ports see appendix C, I/O Port Block Diagrams.
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