HD6432351 Datasheet, PDF (628/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

The method of calculating the value to be set in the bit rate register (BRR) from the operating
frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the
smaller error is specified.
N=
ø
× 10⁶ – 1
1488 × 2^2n–1 × B
Table 14-6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0)
bit/s
9600
ø (MHz)
7.1424 10.00 10.7136 13.00 14.2848 16.00
18.00
20.00
N Error N Error N Error N Error N Error N Error N Error N Error
0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.60
Table 14-7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
ø (MHz)
Maximum Bit Rate (bit/s)
N
n
7.1424
9600
0
0
10.00
13441
0
0
10.7136
14400
0
0
13.00
17473
0
0
14.2848
19200
0
0
16.00
21505
0
0
18.00
24194
0
0
20.00
26882
0
0
The bit rate error is given by the following formula:
Error (%) = (
ø
1488 × 2^2n–1 × B × (N + 1)
× 10⁶ – 1) × 100
608