HD6432351 Datasheet, PDF (938/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

*1
P3_n
*2
Reset
R
Q
D
P3nDDR
C
WDDR3
Reset
R
Q
D
P3nDR
C
WDR3
Reset
R
Q
D
P3nODR
C
WODR3
RODR3
RDR3
SCI module
Serial receive data
enable
RPOR3
Legend
WDDR3
WDR3
WODR3
RDR3
RPOR3
RODR3
n = 2 or 3
: Write to P3DDR
: Write to P3DR
: Write to P3ODR
: Read P3DR
: Read port 3
: Read P3ODR
Notes: 1. Output enable signal
2. Open drain control signal
Serial receive data
Figure C-3 (b) Port 3 Block Diagram (Pins P3₂ and P3₃)
918