HD6432351 Datasheet, PDF (449/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

10.2.5 Timer Status Register (TSR)
Channel 0: TSR0
Channel 3: TSR3
Bit
:
7
6
5
4
—
—
—
TCFV
Initial value :
1
1
0
0
R/W
:
—
—
— R/(W)*
Note: * Can only be written with 0 for flag clearing.
3
TGFD
0
R/(W)*
2
TGFC
0
R/(W)*
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit
:
7
6
5
4
3
TCFD
—
TCFU TCFV
—
Initial value :
1
1
0
0
0
R/W
:
R
— R/(W)* R/(W)* —
Note: * Can only be written with 0 for flag clearing.
2
1
0
—
TGFB TGFA
0
0
0
— R/(W)* R/(W)*
The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR
registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in
hardware standby mode.
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