HD6432351 Datasheet, PDF (725/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 21-8 Timing of On-Chip Supporting Modules (cont)
Condition A: V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_ref = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications
Condition A
Item
Symbol Min Max
WDT
Overflow output
delay time
t _WOVD
— 100
SCI
Input Asynchro- t _Scyc
4
—
clock nous
cycle _Synchro-
6
—
nous
Input clock pulse
width
t _SCKW
0.4 0.6
Input clock rise
t _SCKr
time
— 1.5
Input clock fall
t _SCKf
— 1.5
time
Transmit data
t _TXD
— 100
delay time
Receive data setup t _RXS
time (synchronous)
100 —
Receive data hold t _RXH
time (synchronous)
100 —
A/D
Trigger input setup t _TRGS
converter time
50 —
Condition B
Min Max
— 50
4
—
6
—
0.4 0.6
— 1.5
— 1.5
— 50
50 —
50 —
30 —
Unit Test Conditions
ns Figure 21-26
t _cyc Figure 21-27
t _Scyc
t _cyc
ns Figure 21-28
ns
ns
ns Figure 21-29
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