HD6432351 Datasheet, PDF (220/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

(2) Repeat Mode
Transfer Number Storage
Bit
:
15
14
13
12
11
10
9
8
ETCRH :
Initial value :
*
*
*
*
*
*
*
*
R/W
:
R/W
R/W R/W R/W R/W R/W
R/W R/W
Transfer Counter
Bit
:
7
6
5
4
3
2
1
0
ETCRL :
Initial value :
*
*
*
*
*
*
*
*
R/W
:
R/W
R/W R/W R/W R/W R/W
R/W R/W
*: Undefined
In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and
transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is
performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this
point, MAR is automatically restored to the value it had when the count was started. The DTE bit
in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is
cleared by the user.
ETCR is not initialized by a reset or in standby mode.
7.2.4 DMA Control Register (DMACR)
Bit
:
DMACR :
Initial value :
R/W
:
7
DTSZ
0
R/W
6
DTID5
0
R/W
5
RPE
0
R/W
4
DTDIR
0
R/W
3
DTF3
0
R/W
2
DTF2
0
R/W
1
DTF1
0
R/W
0
DTF0
0
R/W
DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel.
DMACR is initialized to H'00 by a reset, and in standby mode.
200