HD6432351 Datasheet, PDF (611/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Restrictions on Use of DMAC or DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 ø clock cycles after TDR is updated by the DMAC or DTC. Misoperation
may occur if the transmit clock is input within 4 ø clocks after TDR is updated. (Figure 13-22)
• When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant
SCI reception end interrupt (RXI).
SCK
TDRE
Serial data
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t >4 clocks.
Figure 13-22 Example of Clocked Synchronous Transmission by DTC
591