HD6432351 Datasheet, PDF (849/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

IOAR0A—I/O Address Register 0A
H'FEE4
DMAC
Bit
: _{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
IOAR0A :
Initial value : _{* * * * * * * * * * * * * * * *}
Read/Write : _{R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W}
* : Undefined
In short address mode: Specifies transfer source/transfer destination address
In full address mode: Not used
ETCR0A—Transfer Count Register 0A
H'FEE6
DMAC
Bit
: _{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
ETCR0A :
Initial value : _{* * * * * * * * * * * * * * * *}
Read/Write : _{R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W}
Sequential
mode
Idle mode
Normal mode
Transfer counter
Repeat mode
Block transfer
mode
Transfer number storage register
Block size storage register
Transfer counter
Block size counter
* : Undefined
829