HD6432351 Datasheet, PDF (671/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Section 17 RAM
17.1 Overview
The H8S/2350 Series has 2 kbytes of on-chip high-speed static RAM. The RAM is connected to
the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word
data. This makes it possible to perform fast word data transfer.
The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the
system control register (SYSCR).
17.1.1 Block Diagram
Figure 17-1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FFF400
H'FFF402
H'FFF404
H'FFF401
H'FFF403
H'FFF405
H'FFFBFE
H'FFFBFF
Figure 17-1 Block Diagram of RAM
651