HD6432351 Datasheet, PDF (965/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Reset
R
Q
D
PF2DDR
C
WDDRF
Reset
Bus controller
Wait enable
Mode 1/2*/4/5/6*
R
PF₂
Mode 4/5/6*
Q
D
PF2DR
C
WDRF
Mode 1/2*/4/5/6*
RDRF
Bus request output
enable
Bus request output
RPORF
Legend
WDDRF : Write to PFDDR
WDRF : Write to PFDR
RDRF : Read PFDR
RPORF : Read port F
Note: * Modes 2 and 6 only apply to the H8S/2351.
Wait input
LCAS output
enable
LCAS output
Figure C-12 (c) Port F Block Diagram (Pin PF₂)
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