HD6432351 Datasheet, PDF (963/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

C.12 Port F Block Diagram
Reset
Mode 1/2*/4/5/6*
R
Q
D
PF0DDR
C
WDDRF
Reset
Bus controller
BRLE bit
R
PF₀
Q
D
PF0DR
C
WDRF
RDRF
RPORF
Legend
WDDRF : Write to PFDDR
WDRF : Write to PFDR
RDRF : Read PFDR
RPORF : Read port F
Note: * Modes 2 and 6 only apply to the H8S/2351.
Bus request input
Figure C-12 (a) Port F Block Diagram (Pin PF₀)
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