HD6432351 Datasheet, PDF (35/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 1-3 Pin Functions (cont)
Type
Interrupts
Address bus
Data bus
Bus control
Symbol
NMI
IRQ7 to
IRQ0
A₂₃ to
A₀
D₁₅ to
D₀
CS7 to
CS0
AS
RD
HWR
LWR
CAS
Pin No.
TFP-120 FP-128 I/O Name and Function
74
82
Input Nonmaskable interrupt: Requests a
nonmaskable interrupt. When this pin
is not used, it should be fixed high.
28 to 25, 32 to 29, Input
29 to 32 33, 34,
37, 38
Interrupt request 7 to 0: These pins
request a maskable interrupt.
28 to 25,
23 to 16,
14 to 7,
5 to 2
32 to 29,
27 to 20,
18 to 11,
9 to 6
Output Address bus: These pins output an
address.
51 to 48, 57 to 54, I/O
46 to 39, 52 to 45,
37 to 34 43 to 40
Data bus: These pins constitute a
bidirectional data bus.
29, 30, 33, 34,
61, 60, 69, 66,
117 to 120 127, 128,
1, 2
Output
Chip select: Signals for selecting
areas 7 to 0.
82
90
Output Address strobe: When this pin is low,
it indicates that address output on the
address bus is enabled.
83
91
Output Read: When this pin is low, it
indicates that the external address
space can be read.
84
92
Output High write/write enable:
A strobe signal that writes to external
space and indicates that the upper
half (D₁₅ to D₈) of the data bus is
enabled.
The 2CAS type DRAM write enable
signal.
85
93
Output Low write:
A strobe signal that writes to external
space and indicates that the lower
half (D₇ to D₀) of the data bus is
enabled.
116
126
Output Upper column address strobe/column
address strobe:
The 2CAS type DRAM upper column
address strobe signal.
15