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HD6432351 Datasheet, PDF (815/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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MRBâDTC Mode Register B
H'F800âH'FBFF
DTC
Bit
:
Initial value :
Read/Write :
7
6
5
4
3
2
1
0
CHNE DISEL â
â
â
â
â
â
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
â
â
â
â
â
â
â
â
Reserved
Only 0 should be written to these bits
DTC Interrupt Select
0 After a data transfer ends, the CPU interrupt is
disabled unless the transfer counter is 0
1 After a data transfer ends, the CPU interrupt is enabled
DTC Chain Transfer Enable
0 End of DTC data transfer
1 DTC chain transfer
SARâDTC Source Address Register
H'F800âH'FBFF
DTC
Bit
: 23 22 21 20 19
---
43210
---
Initial value : Unde- Unde- Unde- Unde- Unde-
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
fined fined fined fined fined
Read/Write : â â â â â
---
â â ââ â
Specifies transfer data source address
DARâDTC Destination Address Register
H'F800âH'FBFF
DTC
Bit
: 23 22 21 20 19
---
43210
---
Initial value : Unde- Unde- Unde- Unde- Unde-
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
fined fined fined fined fined
Read/Write : â â â â â
---
âââââ
Specifies transfer data destination address
795
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