HD6432351 Datasheet, PDF (881/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

PORTG—Port G Register
H'FF5F
Port G
Bit
:
7
6
5
—
—
—
Initial value : Undefined Undefined Undefined
Read/Write : —
—
—
4
PG4
—*
R
3
PG3
—*
R
2
PG2
—*
R
1
PG1
—*
R
0
PG0
—*
R
Note: * Determined by the state of pins PG₄ to PG₀.
State of port G pins
P1DR—Port 1 Data Register
H'FF60
Port 1
Bit
:
Initial value :
Read/Write :
7
P17DR
0
R/W
6
P16DR
0
R/W
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
Stores output data for port 1 pins (P1₇ to P1₀)
P2DR—Port 2 Data Register
H'FF61
Port 2
Bit
:
Initial value :
Read/Write :
7
P27DR
0
R/W
6
P26DR
0
R/W
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
Stores output data for port 2 pins (P2₇ to P2₀)
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