HD6432351 Datasheet, PDF (775/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-4 Number of States per Cycle
Access Conditions
On-Chip Supporting
Module
External Device
8-Bit Bus
16-Bit Bus
Cycle
On-Chip 8-Bit
Memory Bus
16-Bit
Bus
2-State 3-State 2-State 3-State
Access Access Access Access
Instruction fetch
S_I 1
4
2
4
Branch address read S_J
Stack operation
S_K
Byte data access S_L
2
2
Word data access S_M
4
4
Internal operation S_N 1
1
1
1
Legend
m: Number of wait states inserted into external device access
6 + 2m 2
3+m
6 + 2m
1
1
3+m
1
755