HD6432351 Datasheet, PDF (244/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5,
and 1 in DMABCR, and bit 4 in DMATCR.
Bit 1
WE0B
0
1
Description
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are disabled
(Initial value)
Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR
are enabled
Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits
8, 4, and 0 in DMABCR.
Bit 0
WE0A
0
1
Description
Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled
(Initial value)
Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled
Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the
DMAWER settings. These bits should be changed, if necessary, by CPU processing.
In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.
To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable
B for the channel to be reactivated.
MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When
modifying these registers, the channel for which the modification is to be made should be halted.
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