HD6432351 Datasheet, PDF (675/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Section 18 ROM (H8S/2351 Only)
18.1 Overview
The H8S/2351 has 64 kbytes of on-chip ROM (mask ROM). The ROM is connected to the
H8S/2000 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state,
making possible rapid instruction fetches and high-speed processing.
The on-chip ROM is enabled or disabled by setting the mode pins (MD₂, MD₁, and MD₀) and bit
EAE in BCRL.
18.1.1 Block Diagram
Figure 18-1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'000004
H'000001
H'000003
H'000004
H'00FFFE
H'00FFFF
Figure 18-1 Block Diagram of ROM (H8S/2351)
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