HD6432351 Datasheet, PDF (900/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

SCR1—Serial Control Register 1
H'FF82
SCI1
Bit
:
7
TIE
Initial value :
0
Read/Write : R/W
6
5
RIE
TE
0
0
R/W R/W
4
3
2
1
0
RE MPIE TEIE CKE1 CKE0
0
0
0
0
0
R/W R/W R/W R/W R/W
Clock Enable
0 0 Asynchronous
mode
Synchronous
mode
1 Asynchronous
mode
Synchronous
mode
1 0 Asynchronous
mode
Synchronous
mode
1 Asynchronous
mode
Synchronous
mode
Internal clock/SCK pin functions
as I/O port
Internal clock/SCK pin functions
as serial clock output
Internal clock/SCK pin functions
as clock output*¹
Internal clock/SCK pin functions
as serial clock output
External clock/SCK pin functions
as clock input*²
External clock/SCK pin functions
as serial clock input
External clock/SCK pin functions
as clock input*²
External clock/SCK pin functions
as serial clock input
Notes: 1. Outputs a clock of the same frequency as the bit rate.
2. Inputs a clock with a frequency 16 times the bit rate.
Transmit End Interrupt Enable
0 Transmit end interrupt (TEI) request disabled
1 Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable
0 _{Multiprocessor interrupts disabled}
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When MPB= 1 data is received
1
Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to 1
is received
Receive Enable
0 Reception disabled
1 Reception enabled
Transmit Enable
0 Transmission disabled
1 Transmission enabled
Receive Interrupt Enable
0 Receive data full interrupt (RXI) request and
receive error interrupt (ERI) request disabled
1 Receive data full interrupt (RXI) request and
receive error interrupt (ERI) request enabled
Transmit Interrupt Enable
0 Transmit data empty interrupt (TXI) requests disabled
1 Transmit data empty interrupt (TXI) requests enabled
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