HD6432351 Datasheet, PDF (205/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.10 Bus Release
6.10.1 Overview
The H8S/2350 Series can release the external bus in response to a bus request from an external
device. In the external bus released state, the internal bus master continues to operate as long as
there is no external access.
If an internal bus master wants to make an external access in the external bus released state, or if a
refresh request is generated, it can issue a bus request off-chip.
6.10.2 Operation
In external expansion mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2350 Series.
When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the
address bus, data bus, and bus control signals are placed in the high-impedance state, establishing
the external bus-released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped. Even if a refresh request is generated in the external bus released state, refresh control is
deferred until the external bus master drops the bus request.
If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external
access in the external bus released state, or when a refresh request is generated, the BREQO pin is
driven low and a request can be made off-chip to drop the bus request.
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is
as follows:
(High) External bus release > Internal bus master external access (Low)
If a refresh request and external bus release request occur simultaneously, the order of priority is
as follows:
(High) Refresh > External bus release (Low)
As a refresh and an external access by an internal bus master can be executed simultaneously,
there is no relative order of priority for these two operations.
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