HD6432351 Datasheet, PDF (839/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

PFDDR—Port F Data Direction Register
H'FEBE
Port F
Bit
:
7
6
5
4
3
2
1
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 1, 2, 4 to 6
Initial value :
1
0
0
0
0
0
0
0
Read/Write :
W
W
W
W
W
W
W
W
Modes 3, 7
Initial value :
0
0
0
0
0
0
0
0
Read/Write :
W
W
W
W
W
W
W
W
Specify input or output for individual port F pins
PGDDR—Port G Data Direction Register
H'FEBF
Port G
Bit
:7
6
5
4
3
2
1
0
—
—
— PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
Modes 1, 4, 5
Initial value : _{Undefined Undefined Undefined 1}
0
0
0
0
Read/Write : _—
—
—
W
W
W
W
W
Modes 2, 3, 6, 7
Initial value : _{Undefined Undefined Undefined 0}
0
0
0
0
Read/Write : _—
—
—
W
W
W
W
W
Specify input or output for individual port G pins
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