HD6432351 Datasheet, PDF (911/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

TCSR—Timer Control/Status Register
H'FFBC (W) H'FFBC (R)
WDT
Bit
:7
6
5
4
OVF WT/IT TME
—
Initial value : 0
0
0
1
Read/Write : R/(W)* R/W R/W
—
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W
R/W
R/W
Clock Select
CKS2 CKS1 CKS0 Clock
Overflow period*
(when ø = 20 MHz)
0 0 0 ø/2 (initial value) 25.6µs
1 ø/64
819.2µs
1 0 ø/128
1.6ms
1 ø/512
6.6ms
1 0 0 ø/2048
26.2ms
1 ø/8192
104.9ms
1 0 ø/32768
419.4ms
1 ø/131072
1.68s
Timer Enable
Note: * The overflow period is the time from when TCNT
starts counting up from H'00 until overflow occurs.
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Timer Mode Select
0 Interval timer mode: Sends the CPU an interval timer interrupt request
(WOVI) when TCNT overflows
1 Watchdog timer mode: Generates the WDTOVF signal when
TCNT overflows
Overflow Flag
0 [Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
1 [Setting condition]
Set when TCNT overflows from H'FF to H'00 in interval timer mode
The method for writing to TCSR is different from that for general registers to prevent accidental overwriting.
For details see section 12.2.4, Notes on Register Access.
Note: * Can only be written with 0 for flag clearing.
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