HD6432351 Datasheet, PDF (583/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

• Serial data transmission (asynchronous mode)
Figure 13-5 shows a sample flowchart for serial transmission.
The following procedure should be used for serial data transmission.
Initialization
Start transmission
Read TDRE flag in SSR
TDRE=1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
All data transmitted?
Yes
Read TEND flag in SSR
TEND= 1
Yes
Break output?
Yes
Clear DR to 0 and
set DDR to 1
[1] ^{[1] SCI initialization:}
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
[2]
of 1s is output, and transmission is
enabled.
No
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
[3] Serial transmission continuation
procedure:
No
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
[3]
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC or DTC
is activated by a transmit data
No
empty interrupt (TXI) request, and
data is written to TDR.
[4] Break output at the end of serial
transmission:
No
[4]
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Clear TE bit in SCR to 0
<End>
Figure 13-5 Sample Serial Transmission Flowchart
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