HD6432351 Datasheet, PDF (414/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin
states, as PGDDR and PGDR are initialized. PORTG retains its prior state after a manual reset,
and in software standby mode.
9.14.3 Pin Functions
Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS). The pin
functions are different in modes 1 and 2, modes 3 and 7, and modes 4 to 6. Port G pin functions
are shown in table 9-26.
Table 9-26 Port G Pin Functions
Pin
PG₄/CS0
Selection Method and Pin Functions
The pin function is switched as shown below according to the operating mode
and bit PG4DDR.
Operating
Mode
Modes 1, 2, 4, 5, 6*
Modes 3 and 7*
PG4DDR
0
1
0
1
Pin function PG₄ input pin CS0 output pin PG₄ input pin PG₄ output pin
PG₃/CS1
The pin function is switched as shown below according to the operating mode
and bit PG3DDR.
Operating
Mode
Modes 1, 2, 3, 7*
Modes 4 to 6*
PG3DDR
0
1
0
1
Pin function PG₃ input pin PG₃ output pin PG₃ input pin CS1 output pin
PG₂/CS2
The pin function is switched as shown below according to the operating mode
and bit PG2DDR.
Operating
Mode
Modes 1, 2, 3, 7*
Modes 4 to 6*
PG2DDR
0
1
0
1
Pin function PG₂ input pin PG₂ output pin PG₂ input pin CS2 output pin
Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351.
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