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HD6432351 Datasheet, PDF (452/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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Bit 1âInput Capture/Output Compare Flag B (TGFB): Status flag that indicates the
occurrence of TGRB input capture or compare match.
Bit 1
TGFB
0
1
Description
[Clearing conditions]
(Initial value)
⢠When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0
⢠When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
⢠When TCNT = TGRB while TGRB is functioning as output compare register
⢠When TCNT value is transferred to TGRB by input capture signal while TGRB is
functioning as input capture register
Bit 0âInput Capture/Output Compare Flag A (TGFA): Status flag that indicates the
occurrence of TGRA input capture or compare match.
Bit 0
TGFA
0
1
Description
[Clearing conditions]
(Initial value)
⢠When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0
⢠When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is
1
⢠When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
⢠When TCNT = TGRA while TGRA is functioning as output compare register
⢠When TCNT value is transferred to TGRA by input capture signal while TGRA is
functioning as input capture register
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