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HD6432351 Datasheet, PDF (800/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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Table A-7 Condition Code Modification
Instruction
ADD
ADDS
ADDX
AND
ANDC
BAND
Bcc
BCLR
BIAND
BILD
BIOR
BIST
BIXOR
BLD
BNOT
BOR
BSET
BSR
BST
BTST
BXOR
CLRMAC
HNZ VC
âââââ
â
0â
ââââ
âââââ
âââââ
ââââ
ââââ
ââââ
âââââ
ââââ
ââââ
âââââ
ââââ
âââââ
âââââ
âââââ
ââ ââ
ââââ
Definition
H = Smâ4 · Dmâ4 + Dmâ4 · Rmâ4 + Smâ4 · Rmâ4
N = Rm
Z = Rm · Rmâ1 · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
H = Smâ4 · Dmâ4 + Dmâ4 · Rmâ4 + Smâ4 · Rmâ4
N = Rm
Z = Z' · Rm · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
N = Rm
Z = Rm · Rmâ1 · ...... · R0
Stores the corresponding bits of the result.
No flags change when the operand is EXR.
C = C' · Dn
C = C' · Dn
C = Dn
C = C' + Dn
C = C' · Dn + C' · Dn
C = Dn
C = C' + Dn
Z = Dn
C = C' · Dn + C' · Dn
Cannot be used in the H8S/2350 Series
780
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