HD6432351 Datasheet, PDF (918/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

TIER0—Timer Interrupt Enable Register 0
H'FFD4
Bit
:
7
6
TTGE
—
Initial value :
0
1
Read/Write : _R/W
—
5
4
3
2
1
0
— TCIEV TGIED TGIEC TGIEB TGIEA
0
0
0
0
0
0
—
R/W R/W R/W R/W R/W
TPU0
TGR Interrupt Enable A
0 Interrupt requests (TGIA)
by TGFA bit disabled
1 Interrupt requests (TGIA)
by TGFA bit enabled
TGR Interrupt Enable B
0 Interrupt requests (TGIB)
by TGFB bit disabled
1 Interrupt requests (TGIB)
by TGFB bit enabled
TGR Interrupt Enable C
0 Interrupt requests (TGIC) by
TGFC bit disabled
1 Interrupt requests (TGIC) by
TGFC bit enabled
TGR Interrupt Enable D
0 Interrupt requests (TGID) by TGFD
bit disabled
1 Interrupt requests (TGID) by TGFD
bit enabled
Overflow Interrupt Enable
0 Interrupt requests (TCIV) by TCFV disabled
1 Interrupt requests (TCIV) by TCFV enabled
A/D Conversion Start Request Enable
0 A/D conversion start request generation disabled
1 A/D conversion start request generation enabled
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