HD6432351 Datasheet, PDF (512/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

11.1.4 Registers
Table 11-2 summarizes the PPG registers.
Table 11-2 PPG Registers
Name
Abbreviation R/W
Initial Value Address*¹
PPG output control register
PCR
R/W
H'FF
H'FF46
PPG output mode register
PMR
R/W
H'F0
H'FF47
Next data enable register H
NDERH
R/W
H'00
H'FF48
Next data enable register L
NDERL
R/W
H'00
H'FF49
Output data register H
PODRH
R/(W)*² H'00
H'FF4A
Output data register L
PODRL
R/(W)*² H'00
H'FF4B
Next data register H
NDRH
R/W
H'00
H'FF4C*³
H'FF4E
Next data register L
NDRL
R/W
H'00
H'FF4D*³
H'FF4F
Port 1 data direction register
P1DDR
W
H'00
H'FEB0
Port 2 data direction register
P2DDR
W
H'00
H'FEB1
Module stop control register
MSTPCR
R/W
H'3FFF
H'FF3C
Notes: 1. Lower 16 bits of the address.
2. Bits used for pulse output cannot be written to.
3. When the same output trigger is selected for pulse output groups 2 and 3 by the PCR
setting, the NDRH address is H'FF4C. When the output triggers are different, the
NDRH address is H'FF4E for group 2 and H'FF4C for group 3.
Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by
the PCR setting, the NDRL address is H'FF4D. When the output triggers are different,
the NDRL address is H'FF4F for group 0 and H'FF4D for group 1.
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